(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a novel split-gate flash cell having a self-aligned source with a novel poly-tip.
(2) Description of the Related Art
The performance of EEPROMs is enhanced by providing a protrusion for the floating gate of the split-gate cell. Normally, the protrusion is formed by poly oxidation, that is, by oxidizing the polysilicon of which the floating gate comprises. That is, the oxidized portion of the poly-gate is used as a hard mask to form a protruding, so-called gate bird""s beak, or, a tip, which in turn enhances Fowler-Nordheim (F-N) tunneling for the programming and erasing of an EEPROM cell. However, thick poly is needed in order to grow a thick poly-oxide hard-mask. Thick poly, on the other hand, increases gate coupling ratio (GCR), a parameter which is well-known in the art. Thicker GCR then degrades the programming and erasing function of the cell. Especially, with the fast pace of miniaturization and scaling down of devices, it is becoming more and more difficult to form thick poly-oxides because of the oxide thinning effect. Also, self-alignment to source and isolation regions are becoming difficult. It is disclosed in this invention a method of poly-gate side-wall oxidation which circumvents some of these difficulties.
In general, programming and erasing of an EEPROM cell is accomplished electrically by using Fowler-Nordheim (F-N) tunneling as is well known in prior art. F-N tunneling, in turn, is enhanced usually by providing, what is known as a gate bird""s beak (GBB) at the corner of a gate structure of the memory cell. However, the forming of a GBB must be optimized carefully, for, otherwise, the GBB can encroach under the gate edge and degrade the programmability of submicron memory cells. That is, the dimensions and shape of the GBB, which is described below more in detail in relation to nonvolatile memories, play an important role in transferring current to and fro between the substrate and the floating gate, and hence the charging speed of the memory cell, and the amount of surface current leakage that takes place around and near the bird""s beak. It is disclosed later in the embodiments of the present invention a novel approach to form a polysilicon gate tip (poly-tip) in place of gate bird""s beak for enhanced F-N tunneling.
Among the nonvolatile read only memories, such as masked-ROMs, Electrically Programmable (EP-ROMs), EEPROMs have been known as one type of nonvolatile memory semiconductor devices capable of electrically writing and erasing information. However, EEPROMs require two transistors to operate. In Flash EEPROM, the memory cell includes one transistor, and the contents of all the memory""s cells can be erased simultaneously through the use of an electrical erase signal. Hence, with Flash memory, in addition to gaining speed in having the cells erased much more rapidly, higher levels of integration can be achieved with fewer devices.
The unit cell of an EEPROM memory device is usually comprised of a silicon substrate provided with a source and a drain, and two polysilicon gates; that is, a MOS transistor having a channel defined by the source and drain regions, a floating gate to which there is no direct electrical connection and a control gate with a direct electrical connection. The floating gate is separated from the substrate by an insulating layer of, for example, silicon oxide. The control gate is generally positioned over the floating gate with a layer of insulating material separating the two gates. To program a transistor, electron is injected from the substrate through the insulator and is stored on the floating gate of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed xe2x80x9conxe2x80x9d or xe2x80x9coff.xe2x80x9d xe2x80x9cReadingxe2x80x9d of the cell""s state is accomplished by applying appropriate voltages to the cell source and drain, and to the control gate, and then sensing the amount of charge on the floating gate. To erase the contents of a cell, the programming process is reversed, namely, electrons are removed from the floating gate by transferring them to the control gate through the insulator. A fairly recent technology is xe2x80x9cflashxe2x80x9d memories in which the entire array of memory cells, or a significant subset thereof, is erased simultaneously. Flash EEPROMs combine the advantages of UV-erasable EPROMS and floating-gate EEPROMs. They offer high density, small cell size, the well-known hot-electron writeability of EPROMs, together with the easy reusability, on-board reprogrammability, and electron-tunneling erasure feature of EEPROMs (See S. Wolf, xe2x80x9cSilicon Processing for the VLSI Era,xe2x80x9d vol. 2, Lattice Press, Sunset Beach, Calif., 1990, pp. 632-634.)
As stated earlier, programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim tunneling. Basically, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin oxide layer by means of Fowler-Nordheim tunneling. The tunneling is achieved by raising the voltage level on the control gate to a sufficiently high value of about 12 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, the floating gate can be erased by grounding the control gate and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate. Of critical importance in the tunneling region is the quality and the thinness of the tunneling oxide separating the floating gate from the substrate. Usually a thickness of between about 80 to 120 Angstroms is required to facilitate Fowler-Nordheim tunneling.
A cross section of a conventional Flash EEPROM is shown in FIG. 1. Drain impurity diffusion layer (16) and a source impurity diffusion layer (17) are formed on a main surface of the semiconductor substrate (10) and are spaced from each other by a predetermined distance with a channel region therebetween. The conventional Flash EEPROM further includes a floating gate electrode (13) formed on the channel region with a first gate oxide film (12) therebetween, a control gate electrode (15) formed on the floating gate electrode (13) with an insulating film (14) therebetween, an interlayer thermal oxide film (18) covering the semiconductor substrate (10), floating gate electrode (13) and control gate electrode (15), and an interlayer insulating film (19) covering the interlayer thermal oxide film (18). Gate bird""s beak oxide films (20) are formed at opposite ends of the first gate oxide film (12) and opposite end of the insulating film (14). The interlayer insulating film (19) contains impurity such as boron or phosphorous. The purpose of the interlayer thermal oxide film (18) is to prevent the movement of impurity such as boron of phosphorous of the interlayer insulating film (19) into the semiconductor substrate (10), control gate electrode (15) or floating gate electrode (13) and thus to prevent change of the electrical characteristics thereof.
After the final step of forming the interlayer insulating film (19) to cover the interlayer thermal oxide film (18) shown in FIG. 1, usually heat treatment by a reflow method is carried out to flatten the interlayer insulating film (19). During this process as well as during thermally growing the thermal oxide layer (18) by means of wet oxidation, oxidizer (H2O) penetrates the interlayer insulating film (19) and interlayer thermal oxide film (18). This causes further oxidization between the semiconductor substrate (10) and the ends of the floating gate electrode (13), and between the control gate electrode (15) and the floating gate electrode (13). As a result, the gate bird""s beak oxide films (20) are formed. Consequently, the lower end of the floating gate electrode (13) contacts the gate bird""s beak oxide films (20) so that the lower end of the floating gate electrode (13) is oxidized to a large extent as compared with the other portions.
The gate bird""s beak oxide film (20) can form either at the lower end of the floating gate (13) and the source impurity diffusion layer (17), or at the lower end of the floating gate near the drain impurity diffusion layer (16), or at both locations. In these cases, the conventional xe2x80x9cbeakxe2x80x9d of the bird""s beak is usually long and elongated, thus increasing the size of the cell and at the same time providing paths for current leakage and, therefore, low memory speed.
It is proposed in this invention a method of oxidizing a relatively thin polygate so as to decrease the growth of the protrusion of conventional gate bird""s beak (GBB) to a smaller and sharper tip shown by reference numerals (239) in FIGS. 2a-2n of this invention. It will be known by those skilled in the art that GBB is easily damaged during conventional poly etching where polyoxide is used as a hard mask. To use polyoxide as a hard mask, thick polysilicon is needed in the first place. Such thick poly will increase gate coupling ratio, which has the attendant effect of degrading program and erasing performance of the memory cell. It is disclosed in the present invention that thick polysilicon is not needed because the oxidation is performed on the side-walls of the poly-gate to form the poly-tip. Finally, with the disclosed smaller poly-tip of this invention in comparison with the GBB of prior art, the smaller is the encroachment under the polysilicon edge, and hence the smaller is the impact on the electric-field intensity between the corner edge of the floating gate and the control gate of the completed cell structure, and thus faster is the memory speed. (See S. Wolf and R. N. Tauber, xe2x80x9cSilicon Processing for the VLSI Era,xe2x80x9d vol. 2, Lattice Press, Sunset Beach, Calif., 1990, p. 438). It will also be appreciated that the smaller the bird""s beak, the smaller is the overall size of the memory cell contributing to the increased speed of the memory.
Various methods of forming split-gate flash memory cell can be found in prior art. Hong, in U.S. Pat. No. 5,495,441 discloses a split-gate memory cell having a vertical isolation gate and a process for making it. By use of a vertical isolation, Hong is able to obtain smaller size cell, hence denser memory array. Ahn, on the other hand, discloses in U.S. Pat. No. 5,716,865, a method of making split-gate flash EEPROM cell by separating the tunneling region from the channel. The flash EEPROM cell of the invention is capable of preventing the degradation of the tunnel oxide film of the cell due to the band-to-band tunneling and the secondary hot carrier which are generated by a high electric field formed at the overlap region between the junction region and the gate electrode when programming an erasure operations are performed by a high voltage to the structure in which the tunneling region is separated from the channel with a thick insulation film. A process for trench-isolated self-aligned split-gate EEPROM transistor and memory array is disclosed by Hazani in U.S. Pat. No. 5,162,247 where the process results in a structure that allows programming and erasure by electron tunneling only.
More generally, Ashida of U.S. Pat. No. 5,262,655 shows a method of forming an SRAM having a thermal oxide spacer that round the top of the polygate, rather than sharpening it. Wang of U.S. Pat. No. 5,597,751 discloses a method of forming a memory cell structure in a semiconductor substrate that does not have a shorting problem between a floating gate and a source/drain region of the substrate by depositing a thick spacer oxide layer on top of the floating gate and the source/drain region to a sufficient thickness such that electrical insulation is provided therebetween to prevent the occurrence of a short or the formation of a silicide bridge. Gill, et al., in U.S. Pat. No. 5,173,436 use a floating gate transistor with or without a split-gate to construct EEPROM with trench-isolated bitlines.
The present invention discloses a split-gate flash memory cell having a self-aligned source and a sharp poly-tip, without the need for thick poly and no oxide thinning effect.
It is therefore an object of this invention to provide method of forming a novel split-gate flash memory cell with a thin poly-tip.
It is another object of the present invention to provide a method of forming a split-gate memory cell with a thin poly-gate, and without oxide thinning effect.
It is still another object of this invention to provide a method of forming a self-aligned source line in a split-gate flash memory cell.
It is yet another object of this invention to provide a split-gate memory cell with a novel poly-tip for enhanced F-N tunneling.
These objects are accomplished by providing a semiconductor substrate having active and passive regions defined; performing voltage threshold adjustment implantation; forming a gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide layer; forming a first nitride layer over said first polysilicon layer (poly-1); forming a shallow trench ST-photomask over said first nitride layer; forming said shallow trench in said substrate by etching said first nitride layer, first polysilicon layer, gate oxide layer and said substrate; removing said ST-photomask; depositing a first oxide layer over said substrate including said shallow trench; performing chemical mechanical polishing of said first oxide layer over said substrate; removing said first nitride layer; forming a second oxide layer over said substrate; depositing a second nitride layer over said second oxide layer; forming a poly-1 photomask over said second nitride layer; forming openings in underlying said second nitride layer, said second oxide layer and first polysilicon layer through patterns in said poly-1 photomask to form a floating gate structure; removing said poly-1 photomask; performing oxidation of said first polysilicon layer to form a novel poly-tip for said floating gate; forming a hot temperature oxide (HTO) layer over said substrate including said poly-tip and floating gate; forming a second polysilicon layer (poly-2) over said HTO layer; forming a poly-2 photomask over said second polysilicon layer; etching and patterning said second polysilicon layer through said poly-2 photomask to form a control gate; removing said poly-2 mask; forming a self-aligned source (SAS)-photomask over said substrate including said poly-2 layer; etching through said SAS-mask and removing said oxide in said shallow trench; performing ion implantation through said patterning in said second poysilicon layer to form source regions in said substrate; removing said SAS-mask; performing source drive; forming a conformal oxide layer over said substrate; forming oxide spacers; performing ion implantation to form drain regions in said substrate; forming interlevel dielectric layer over said substrate; forming contact holes in said interlevel dielectric layer; forming metal in said contact holes; and etching back excess metal over said substrate in preparation for performing the remaining process steps in the manufacture of said flash split-gate memory device.
These objects are accomplished further by providing a semiconductor substrate having active and passive regions defined; a shallow trench isolation formed in said substrate; a floating gate structure further comprising a first polysilicon layer, an oxide layer on top, which turn is covered by a silicon nitride layer formed on said substrate; a novel poly-tip formed of said floating gate structure; a hot temperature oxide (HTO) layer covering said floating gate structure, including said poly-tip; a control gate formed over said HTO layer serving as inter-gate poly; oxide spacers formed over said sidewalls of said floating gate and said control gate; a self-aligned source line formed in said substrate; source and drain regions in said substrate; and a metal plug in a contact hole contacting said source region.